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ATAN Technology, Inc.
AT8989UP 9 port 10/100 Mb/s Single Chip Ethernet Switch Controller
Preliminary Data Sheet
Revision 1.1 Feb 2002
Revision 1.1 9 port 10/100Mb/s Single Chip Switch Controller AT8989UP
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ATAN Technology, Inc.
Revision History
Revision Date April/2001 May/2001
Revision 0.1 0.2
Description First ATAN version Change RXP, RXN, TXP, TXN Change hardware Setting pin from A1 version 1. ENDC16 Swap with Dual Color setting EEPROM 0x12h bit 15..
July/2001
0.3
2. Aging hardware setting change to EEPROM 0x10h bit7. Port7 FX select change to TXER power on latch. 3. At Dual Speed mode each port support 100/10 Full/Half Separate Data Sheet from AT8989P 1. Remove PHY Register from Data Sheet 2. Add AT8989UP 16 port application note in 3.5 3. Add EEPROM read explain in Dupcol1 pin. 4. Modify LED display pin description. 1. Add eeprom register 0x11h defaulted value as 0xff00h 2. Support By-pass Mode, register 0x11h bit5 3. Support Port-Base VLAN as default setting, Registger 0x11h Bit5 4. Special address forwarding 01 80 C2 00 00 00 DA Forwarding 01 80 C2 00 00 01 DA Filtering 01 80 C2 00 00 02 ~ 01 80 C2 00 00 0F DA Forwarding 5. Support Maximum Packet size as Bypass mode : Tag packet 1522Byte, Untag packet 1522byte Non-bypass mode : Tag packet 1526byte, Untag packet 1522byte 1. Remove "HubbingSwitch" mode description..
Aug/2001 Sep/2001
0.4 0.9
Feb/2002
1.0
Feb/2002
1.1
Notice: This document contains preliminary information on new products under development. The specifications are subject to change without any further notice. Please contact ATAN sales to ensure the updated specifications before finalizing your own design.
ATAN may make changes to specifications and product descriptions at any time without any notice. Copyright (c) ATAN Technology, Inc. April 2000. Third party brands and names are the property of their respective owners.
Revision 1.1 9 port 10/100Mb/s Single Chip Switch Controller AT8989UP
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ATAN Technology, Inc.
1. Introduction
1.1 General Descriptions
The AT8989UP is a high performance, low cost, highly integration (Controller, PHY and Memory) eight-port 10/100 Mbps TX/FX plus one 10/100/Expansion (1.6Gbps) port Ethernet switch controller with all ports supporting 10/100 Mbps Full/Half duplex and 1.6Gbps Expansion port support Full Duplex switch function. The AT8989UP is intended for applications to stand alone bridge for low cost SOHO market such as 8port plus one 100/10 FX or CPU and 16port Switch. AT8989UP provides advanced function such as: 802.1p(Q.O.S.), 802.1q(VLAN), Port MAC address Locking, TP Auto MDIX , 25M Crystal & Extra ninth port(Expansion/MII/GPSI) function to meet customer request on Switch demand. The AT8989UP also supports Back-Pressure in Half-Duplex mode and 802.3x Flow Control Pause packet in Full-Duplex mode to prevent packet lost when buffer full. When Back Pressure is enabled, and there is no receive buffer available for the incoming packet, the AT8989UP will issue a JAM pattern on the receiving port in Half Duplex mode and transmit the 802.3x Pause packet back to receiving end in Full Duplex mode. The built-in 1Mbit SRAM used for packet buffer and address learning table is divided into 256 bytes/block to achieve the optimized memory utilization through complicated link list on packets with various lengths. AT8989UP also supports Port-Base, VLAN and IP TOS field checking for priority mapping. User can be easy to set as different priority mode in individual port, through a small low-cost micro controller to initialize or on-the-fly to configure. Each output port supports four queues in the way of fixed 8:4:2:1 fairness queuing to fit the bandwidth demand on various types of packet such as Voice, Video and data. 802.1Q, Tag/Untag, and up to 16 groups of VLAN also is supported. AT8989UP will learn the last 4 bits of VLAN ID. An intelligent address recognition algorithm makes AT8989UP to recognize up to 2048 different MAC addresses and to enable filtering and forwarding at full wire speed. Port MAC address Locking function is also supported by AT8989UP for customer to use on building Internet access to prevent multiple users share the same single port traffic.
1.2 Features
Supports eight 10M/100M auto-detect Half/Full duplex switch ports with TX/FX interfaces and one universal port. This ninth port can be configured to be a GPSI interface, MII interface, and 1.6Gbps Expansion interface used as proprietary extension bus for cascading to wire -speed 16 port switch applications. Built-in 16Kx64 SRAM. Supports 2048 MAC addresses table. Supports four queues for QOS at fixed 8:4:2:1 rate. Supports Port-Based, 802.1p VLAN & IP TOS priority. Supports Store & Forward architecture and performs forwarding and filtering at non-blocking full wire speed. Supports buffer allocation with 256 bytes per block Supports Aging function Enable/Disable. Supports per port Single/Dual color mode with Power On auto diagnostic. Supports 802.3x Flow Control pause packet for Full Duplex in case buffer is full. Supports Back Pressure function for Half Duplex operation in case buffer is full. Supports packet length up to 1522 bytes. Broadcast Storming Filter function. One Trunk Port with 400M bandwidth formed by fixed two 10/100 ports.
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Supports Port_base and 802.3Q VLAN. Up to 16 VLAN groups is supported by the last four bits of VLAN ID. Supports TP interface Auto MDIX function for auto TX/RX swap. Port7 could be strapping pin-setting as TX or FX mode. 25M Crystal only for whole system. Output 100M (Expansion), 50M (RMII), 25M (MII) & 10M (GPSI) clock for different applications. 208 QFP package with 2.25V/3.3V power supply.
1.3 Applications
AT8989UP in 208-pin PQFP: A. 8 10/100 MDIX TX/FX + FX/CPU Port. MII AT8989UP
8 10/100 MDIX TX/FX
B. 16-port Smart Switch with two AT8989UPs by 1.6Gbps Expansion bus, Any group of port-base VLAN, Trunking with console port. 1.6Gbps Expansion bus AT8989UP
8 10/100 MDIX TX/FX
AT8989UP
8 10/100 MDIX TX/FX
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2. Pinout
2.1 8 TP/FX PORT+ Expansion/MII/GPSI PORT 208 Pin Diagram
155 156 GRXD3 154 152 153 GRXD1 150 151 149 148 147 145 146 144 143 142 140 141 138 139 136 137 134 135 133 132 131 129 130 128 126 127 124 125 123 122 121 119 120 118 116 117 115 113 114 111 112 110 109 108 106 107 105
GRXD2 NC
NC
GNDO
LNKACT0 GNDO
LNKACT1
LNKACT3 LNKACT2
GNDIK VCC2IK
LNKACT4
LNKACT6 LNKACT5
LNKACT7
VCC3O VCC3O
GNDO
CFG0 GNDO
EDO CKO25M
GNDIK
VCC2IK GNDIK
VCC2IK
EECS EESK (XOVEN)
EDI (DUAL COLOR)
GCRS(TEST1) GCOL(TEST2)
VCC2IK GNDIK
GRXD0 (TEST0)
GRXDV(LNK1M8) NC
NC
VCC3O GRXCLK
VCC3O
GNDO VCC3O
GNDO
SCAN_EN GNDO
TXCP8 GRXER
GTXEN(PHYAS0)
VCC2IK VCC2IK
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
GNDO GNDO VCC3O VCC3O GRXD4 GRXD5 GRXD6 GRXD7 GNDO GNDO DUPCOL7 DUPCOL6 DUPCOL5 DUPCOL4 (DUPCOL_P7) GNDO GNDO VCC3O VCC3O DUPCOL3 (DUPCOL_P6) DUPCOL2 (DUPCOL_P4)
GNDIK GNDIK
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
(GFCEN) GTXD0 (P7FX) GTXER VCC2IK GTXCLK GNDIK GNDIK GTXD1 GTXD2 GTXD3 GNDO GNDO VCC3O VCC3O GTXD4 GTXD5 GTXD6 GTXD7 GNDO GNDO LDSPD7 LDSPD6 LDSPD5 (SPD_P7) LDSPD4 GNDO GNDO
DUPCOL1 (DUPCOL_P2) (PHYAS1) DUPCOL0 (DUPCOL_P0) (RECANEN) MDC MDIO BONDG VCC2IK VCC2IK VCC2IK GNDIK GNDIK GNDIK RC XI XO VCCPLL GNDPLL GNDPLL CONTROL VREF GNDRG GNDBIAS RTX VCCBIAS VCCRG VCCA2 TXP0 TXN0 GNDA GNDA RXP0 RXN0 VCCAD VCCAD RXN2 RXN5 VCCAD VCCA2 VCCA2 NC VCCA2 TXP3 TXP4 VCCA2 VCCA2 TXP6 VCCA2 NC GNDA 4 3 GNDA GNDA GNDA NC GNDA RXP3 GNDA NC NC GNDA GNDA NC GNDA GNDA GNDA TXN6 RXP6 GNDA RXN1 RXN3 RXN4 RXP4 RXN6 TXP1 TXN1 TXN2 TXP2 TXN3 TXN4 TXP5 TXN5 RXP1 RXP2 RXP5
AT8989UP-208
VCC3O VCC3O (SPD_P6) LDSPD3 (SPD_P4) LDSPD2 VCC2IK VCC2IK GNDIK GNDIK (SPD_P2) LDSPD1 (SPD_P0) LDSPD0 CFG1 TEST VCC2IK VCC2IK GNDIK GNDIK GNDSUBA VCCA2 TXP7 TXN7 GNDA GNDA RXP7 RXN7 VCCAD
NC
NC
10 9
12 11
13
14
16 15
18 17
20 19
22 21
23
24
25
26
27
28
29
31 30
34 33 32
36 35
38 37
40 39
41
43 42
45 44
46
48 47
49
51 50
52
9 port 10/100Mb/s Single Chip Switch Controller
2 1
6 5
8 7
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2.2 Pin Description
AT8989UP-208 PINS( 8TP/FX+Expan/MII/GPSI port) Pin Type I: Input, O: Output, I/O: Bi-directional, PU : Internal Pull UP, OD: Open drain, SCHE: Schmitt Trigger
PD : Internal Pull Down,
2.25V/3V: 2.25V with 3.3V tolerance
Defaulted configuration of AT8989UP : Full-deplex, 100Mb/s, MDIX Off, auto-negotiation On, flow-control On, All TX mode, 8 TX+expansion_bus mode.
Pin # 67, 135
Pin Name CFG[1:0]
Pin Type I, TTL
Pin Description
206, 2, 16 20, 34, 38 51, 55 207, 1, 17 19, 35, 37 52, 54 202, 7, 11 25, 29, 43 46, 59 203, 6, 12 24, 30, 42 47, 58 102
RXP[0:7]
Chip configuration, 2pins Configuration of Pin-out. CFG[1:0] Description 01 8 port and 1 GPSI interface 10 8 port and 1 MII interface 11 8 port and 1 Expansion bus interface for 16port application Twisted Pair Interface, 32 pins I, Twisted Pair Receive Input Positive. Analog I, Twisted Pair Receive Input Negative. Analog O, Twisted Pair Transmit Output Positive. Analog O, Twisted Pair Transmit Output Negative. Analog
RXN[0:7]
TXP[0:7]
TXN[0:7]
94, 95, 96 86, 87, 88, 89 101
156, 154, 152, 121
Ninth Port( MII, GPSI & Expansion) Interfaces, 26pins I/O, MII/GPSI/Expansion_bus transmit data 0 / Global Flow Control 8mA Enable. PU MII transmit data 0/Global Flow Control Enable. At power-on-reset, latched as Flow control setting "1" to enable flow-control ( defaulted ), "0" to disable flow-control. For output mode, acts as MII transmit data TXD or Expansion bus TXD0 Synchronous to the rising edge of TXCLK Internally Pull-up GTXD[3:1] O, Expansion/MII Transmit Data bit 3~1 8mA Synchronous to the rising edge of GTXCLK at Expansion mode. GTXD[7:4] O Expansion Port Transmit Data bit 7~4 8mA Synchronous to the rising edge of GTXCLK. GTXER I/O GTXER(Expansion bus, MII transmit error )/P7FX /P7FX 8mA Power-on-reset, Signals latched as TX ("0"), FX("1") mode at Port7. PD Internal pull down as Port7 TX mode. GRXD[3:0] I Expansion Port Receive Data bit 3 ~ 0 PD During power on reset, GRXD0 value will be latched by AT8989UP at the rising edge of RESETL for TSEL0. Internal pull down. GTXD[0] /GFCEN
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164, 163, 162, 161
GRXD[7:4]
I PD
177,
DUPCOL1/PHYAS1,
I/O PD 8mA
I/O PD, 8mA
107
GTXEN/ PHYAS0
119
GRXDV
I
109 125
GRXER GCOL
I PD I PD I, PD O 16mA I I I/O, 8mA
Expansion Port Receive Data bit 4 ~ 0 In configuration mode, (8+1MII, CFG1:0=1:0), GRXD7~5 will be used for MII port SPDTEN, LNKFAIL and DPHALF status inputs with internal pull down value.. Port1 DupCol LED/ PHYAS1 (177) GTXEN(Expansion). PHYAS0 (107) During power on reset, strapping value will be latched by AT8989UP at the rising edge of RESETL as PHY start address select. Internal pull down. PHYAS1/S0 MII PHY Address E2PRM 00 08h Master 01 09h Slave0 1x 18h Not used For two of AT8989UP as 16port application : Master: AT8989UP will read 93C46/66 EEPROM first Bank.(00h~27h). Slave0: AT8989UP will read 93C66 EEPROM second Bank.(40h~67h). When Dupcol1 connect a pull down resister to read EEPROM this signal will become active high on LED display. DUPCOL1, Duplex Collision LED for port1 output If pulled low , then acted as active high to drive "1" for full-duplex indication "0" for half-duplex and "blinking" for collision indication If pulled high, then acted as active low to drive "1" for half-duplex and "blinking" for collision indication "0" for full-duplex indication GTXEN output, Expansion bus/GPSI/MII transmit enable. "1" to indicate transmit enable, "0" to indicate transmit disable. Expansion port Receive Data Valid In configuration mode 1 (8 + 1 GPSI), this pin will be used for GPSI link status input Expansion Port Receive Error MII Port Collision input During power on reset, GCOL value will be latched by AT8989UP at the rising edge of RESETL for TSEL2. Internal pull down Expansion/MII Port Carrier Sense During power on reset, GCRS value will be latched by AT8989UP at the rising edge of RESETL for TSEL1. Internal pull down Expansion Port clock Output Expansion Port or MII Port Receive Clock Input MII Port Transmit clock Input LED Interface, 24 pins LINK/Activity LED. Active low "1" indicates no link activity on cable "0" indicates link okay on cable, but no activity and signals on idle stage. "blinking" indicates link activity on cable. Duplex/Collision LED. Active low
Revision 1.1
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GCRS
99 117 108 140, 141, 142, 143, 146, 147, 148, 149 167, 168,
GTXCLK GRXCLK TXCLK8 LNKACT[7:0]
DUPCOL[7:2]
O,
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169, 170, 175, 176, 177, 178
8mA
177 178
DUPCOL[1] DUPCOL0/ANEN
O, 8mA I/O, 8mA PU O, 16mA
83, 82, 81 80, 75, 74 69, 68 133 127
LDSPD[7:0]
"1" for half-duplex and "blinking" for collision indication "0" for full-duplex indication DUPCOL0 will be power on latch value as all port Auto Negotiation capability recommended value. Internal pull high as Auto Negotiation capability. Add pull down will disable all port Auto Negotiation capability. Duplex/Collision LED[1]. See "9thport interface" pin description for details. Duplex/Collision LED[0] / AutoNegotiation Enable. On power-on-reset, latched as Auto Negotiation capability for all ports. "1" to enable AutoNegotiation ( defaulted by pulled up internally ), "0" to disable AutoNegotiation. Speed LED[7:0]. Used to indicate corresponding port's speed status. "0" for 100Mb/s, "1" for 10Mb/s
EEDO EECS
128
EECK/ XOVEN
126
EEDI/Dual Color
180 179
MDIO MDC
134 194 198 195 188 189 190 181
CKO25M Control RTX VREF RC XI XO BONDG
EEPROM/Management Interface,6 pins I, EEPROM Data Output. Serial data input from EEPROM. This pin is TTL, PU internal pull-up. O, EEPROM Chip Select. This pin is active high chip enable for 4mA, EEPROM. When RESETL is low, it will be Tri-state. This pin is internal PD pull-down. I/O, Serial Clock. This pin is clock source for EEPROM. When RESETL is 4mA low, it will be tri-state. This pin is internally pull-down. PD XOVEN. On power-on-reset, latched as P7~0 Auto MDIX enable or not. "1" to disable MDIX ( defaulted ), "0" to enable MDIX. Suggest externally pull up to enable MDIX for all ports. O, EEPROM Serial Data Input. This pin is output for serial data transfer. 4mA When RESETL is low, it will be tri-state. This pin is internal pull-down. PD Dual Color. On power-on-reset, latched as Dual Color mode or not. "0" to set Single color mode for LED. "1" to set Dual Color mode for LED. I/O, Management Data. This pin is in-out to PHY. When RESETL is low, 8mA this pin will be tri-state. O, Management Data Clock. This pin output 1MHz clock to drive PHY 8mA and access corresponding speed and duplex data through MDIO. MISC., 11 pins O, 10M Clock Output For 1M8 port configuration, 50M output for DSHUB 8mA slave and 25M Clock Output for others. FET Control Signal. The pin is used to control FET for 3.3V to 2.5V O Regulator. Analog TX Resistor. Analog Analog Reference Voltage. I, RC Input For Power On reset. SCHE I, 25M Crystal Input. 25M Crystal Input. Variation is limited to +/Analog 50ppm. O, 25M Crystal Output. When connected to oscillator, this pin should left Analog unconnected. I, TTL Must connect to Ground. Power/Ground., 98 pins
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3, 5, 13, 15, 21, 23, 31, 33, 39, 41, 48, 50, 56, 57, 204, 205 8, 10, 26, 28, 44, 45, 60, 201 18, 36, 53, 208 61 197 199 192, 193 191 62, 63, 70, 71, 97, 98, 103, 104, 123, 131, 132, 144 185, 186, 187 64, 65, 72, 73, 100, 105, 106, 122, 129 130, 145, 182 183, 184 78, 79, 84, 85, 92, 93, 111, 112, 113 136, 137, 150 151, 157, 158 165, 166, 171 172 76, 77, 90, 91, 114, 115 116, 138, 139 159, 160, 173, 174 200 196 110
GNDA
Ground Used by AD Block.
VCCA2
2.25V, Power Used by TX Line Driver.
VCCAD GNDSUBA GNDBIAS VCCBIAS GNDPLL VCCPLL GNDIK
3.3V, Power Used by AD Block. Ground Used by Analog Substrate Ground Used by Bias Block 3.3V, Power Used by Bias Block. Ground used by PLL 2.25V, Power used by PLL Ground Used by Digital Core
VCCIK
2.25V, Power Used by Digital Core
GNDO
Ground Used by Digital Pad
VCC3O
3.3V, Power Used by Digital Pad.
VCCRG GNDRG GND
I, TTL
3.3V, Power used of Regulator Ground used of Regulator Scan Enable. This pin will be used as the scan enable input for testing. Connect to GND at normal application. NC pin., 12 pins Not Connect.
4, 9, 14, 22, 27, 32, 40, 49, 118 120, 153, 155
NC
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3. Description
3.1 Functional Descriptions
The AT8989UP integrates eight 100Base-X physical sub-layer (PHY), 100Base-TX physical medium dependent (PMD) transceivers, eight complete 10Base-T modules, 8 port 100/10 switch controller and one 1.6G MAC and memory into a single chip for both 10 Mbps, 100 Mbps Ethernet switch operation. It also supports 100Base-FX operation through external fiber-optic transceivers. The device is capable of operating in either Full Duplex mode or Half-Duplex mode in either 10 Mbps or 100 Mbps operation. 1.6G Expansion port only supports Full Duplex. Operational modes can be selected by hardware configuration pins, software settings of management registers, or determined by the on-chip auto negotiation logic. The AT8989UP consists of three major blocks: 10/100M PHY Block Switch Controller Block Built-in 16Kx64 SSRAM
3.2 10/100M PHY Block
The 100Base-X section of the device implements he following functional blocks : 100Base-X physical coding sub-layer (PCS) 100Base-X physical medium attachment (PMA) Twisted-pair transceiver (PMD) The 100Base-X and 10Base-T sections share the following functional blocks : Clock synthesizer module MII Registers IEEE 802.3u auto negotiation The interfaces used for communication between PHY block and switch core is MII interface. Auto MDIX function is supported in this block. This function can be Enable/Disable by hardware pin. 3.2.1 100Base-X Module The AT8989UP implements 100Base-X compliant PCS and PMA and 100Base-TX compliant TP-PMD as illustrated in Figure 2. Bypass options for each of the major functional blocks within the 100Base-X PCS provides flexibility for various applications. 100 Mbps PHY loop back is included for diagnostic purpose. 3.2.2 100Base-X Receiver The 100Base-X receiver consists of functional blocks required to recover and condition the 125 Mbps receive data stream. The AT8989UP implements the 100Base-X receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125 Mbps receive data stream may originate from the on-chip twisted-pair transceiver in a 100Base-TX application. Alternatively, the receive data stream may be generated by an external optical receiver as in a 100Base-FX application. The receiver block consists of the following functional sub-blocks :
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A/D Converter Adaptive Equalizer and timing recovery module NRZI/NRZ and serial/parallel decoder De-scrambler Symbol alignment block Symbol Decoder Collision Detect Block Carrier sense Block Stream decoder block 3.2.2.1 A/D Converter High performance A/D converter with 125M sampling rate converts signals received on RXP/RXN pins to 6 bits data streams; besides it possess auto-gain-control capability that will further improve receive performance especially under long cable or harsh detrimental signal integrity. Due to high pass characteristic on transformer, built in base-line-wander correcting circuit will cancel it out and restore its DC level. 3.2.2.2 Adaptive Equalizer and timing Recovery Module All digital design is especial immune from noise environments and achieves better correlation between production and system testing. Baud rate Adaptive Equalizer/Timing Recovery compensates line loss induced from twisted pair and tracks far end clock at 125M samples per second. Adaptive Equalizer implemented with Feed forward and Decision Feedback techniques meet the requirement of BER less than 10-12 for transmission on CAT5 twisted pair cable ranging from 0 to 120 meters. 3.2.2.3 NRZI/NRZ and Serial/Parallel Decoder The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned to 4B/5B code group's boundary. 3.2.2.4 Data De-scrambling The de-scrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and locking its deciphering Linear Feedback Shift Register (LFSR) to the state of the scrambling LFSR. Upon achieving synchronization, the incoming data is XORed by the deciphering LFSR and de-scrambled. In order to maintain synchronization, the de-scrambler continuously monitors the validity of the unscrambled data that it generates. To ensure this, a link state monitor and a hold timer are used to constantly monitor the synchronization status. Upon synchronization of the de-scrambler the hold timer starts a 722 us countdown. Upon detection of sufficient idle symbols within the 722 us period, the hold timer will reset and begin a new countdown. This monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. If the link state monitor does not recognize sufficient unscrambled idle symbols within 722 us period, the de-scrambler will be forced out of the current state of synchronization and reset in order to re-acquire synchronization. 3.2.2.5 Symbol Alignment The symbol alignment circuit in the AT8989UP determines code word alignment by recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the de-scrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary.
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3.2.2.6 Symbol Decoding The symbol decoder functions as a look-up table that translates incoming 5B symbols into 4B nibbles as shown in Table 1. The symbol decoder first detects the /J/K symbol pair proceeded by idle symbols and replaces the symbol with MAC preamble. All subsequent 5B symbols are converted to the corresponding 4B nibbles for the duration of the entire packet. This conversion ceases upon the detection of the /T/R symbol pair denoting the end of stream delimiter (ESD). The translated data is presented on the internal RXD[3:0] signal lines with RXD[0] represents the least significant bit of the translated nibble. 3.2.2.7 Valid Data Signal The valid data signal (RXDV) indicates that recovered and decoded nibbles are being presented on the internal RXD[3:0] synchronous to receive clock, RXCLK. RXDV is asserted when the first nibble of translated /J/K is ready for transfer over the internal MII. It remains active until either the /T/R delimiter is recognized, link test indicates failure, or no signal is detected. On any of these conditions, RXDV is de-asserted. 3.2.2.8 Receive Errors The RXER signal is used to communicate receiver error conditions. While the receiver is in a state of holding RXDV asserted, the RXER will be asserted for each code word that does not map to a valid code-group. 3.2.2.9 100Base-X Link Monitor The 100Base-X link monitor function allows the receiver to ensure that reliable data is being received. Without reliable data reception, the link monitor will halt both transmit and receive operations until such time that a valid link is detected. The AT8989UP performs the link integrity test as outlined in IEEE 100Base-X (Clause 24) link monitor state diagram. The link status is multiplexed with 10 Mbps link status to form the reportable link status bit in serial management register 1h, and driven to the LNKACT pin. When persistent signal energy is detected on the network, the logic moves into a Link-Ready state after approximately 500 us, and waits for an enable from the auto negotiation module. When receive, the link-up state is entered, and the transmission and reception logic blocks become active. Should auto negotiation be disabled, the link integrity logic moves immediately to the link-up state after entering the link-ready state. 3.2.2.10 Carrier Sense Carrier sense (CRS) for 100 Mbps operation is asserted upon the detection of two noncontiguous zeros occurring within any 10-bit boundary of the received data stream. The carrier sense function is independent of symbol alignment. In switch mode, CRS is asserted during either packet transmission or reception. For repeater mode, CRS is asserted only during packet reception. When the idle symbol pair is detected in the received data stream, CRS is de-asserted. In repeater mode, CRS is only asserted due to receive activity. CRS is intended to encapsulate RXDV. 3.2.2.11 Bad SSD Detection A bad start of stream delimiter (Bad SSD) is an error condition that occurs in the 100Base-X receiver if carrier is detected (CRS asserted) and a valid /J/K set of code-group (SSD) is not received. If this condition is detected, then the AT8989UP will assert RXER and present RXD[3:0] = 1110 to the internal MII for the
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cycles hat correspond to received 5B code-groups until at least two idle code-groups are detected. Once at least two idle code groups are detected, RXER and CRS become de-asserted. 3.2.2.12 Far-End Fault Auto negotiation provides a mechanism for transferring information from the Local Station to the link Partner that a remote fault has occurred for 100Base-TX. As auto negotiation is not currently specified for operation over fiber, the far end fault indication function (FEFI) provides this capability for 100Base-FX applications. A remote fault is an error in the link that one station can detect while the other cannot. An example of this is a disconnected wire at a station's transmitter. This station will be receiving valid data and detect that the link is good via the link integrity monitor, but will not be able to detect that its transmission is not propagating to the other station. A 100Base-FX station that detects such a remote fault may modify its transmitted idle stream from all ones to a group of 84 ones followed by a single 0. This is referred to as the FEFI idle pattern. 3.2.3 100Base-TX Transceiver AT8989UP implements a TP-PMD compliant transceiver for 100Base-TX operation. The differential transmit driver is shared by the 10Base-T and 100Base-TX subsystems. This arrangement results in one device that uses the same external magnetic for both the 10Base-T and the 100Base-TX transmission with simple RC component connections. The individually wave-shaped 10Base-T and 100Base-TX transmit signals are multiplexed in the transmission output driver selection. 3.2.3.1 Transmit Drivers The AT8989UP 100Base-TX transmission driver implements MLT-3 translation and wave-shaping functions. The rise/fall time of the output signal is closely controlled to conform to the target range specified in the ANSI TP-PMD standard. 3.2.3.2 Twisted-Pair Receiver For 100Base-TX operation, the incoming signal is detected by the on-chip twisted-pair receiver that consists of a differential line receiver, an adaptive equalizer and a base-line wander compensation circuits. The AT8989UP uses an adaptive equalizer that changes filter frequency response in accordance with cable length. The cable length is estimated based on the incoming signal strength. The equalizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable. 3.2.4 10Base-T Module The 10Base-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loop back, jabber, wave shaper, and link integrity functions, as defined in the standard. Figure 3 provides an overview for the 10Base-T module. The AT8989UP 10Base-T module is comprised of the following functional blocks: Manchester encoder and decoder Collision detector Link test function Transmit driver and receiver Serial and parallel interface Jabber and SQE test functions
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Polarity detection and correction
3.2.4.1 Operation Modes The AT8989UP 10Base-T module is capable of operating in either half-duplex mode or full-duplex mode. In half-duplex mode, the AT8989UP functions as an IEEE 802.3 compliant transceiver with fully integrated filtering. The COL signal is asserted during collisions or jabber events, and the CRS signal is asserted during transmit and receive. In full duplex mode the AT8989UP can simultaneously transmit and receive data. 3.2.4.2 Manchester Encoder/Decoder Data encoding and transmission begins when the transmission enable input (TXEN) goes high and continues as long as the transceiver is in good link state. Transmission ends when the transmission enable input goes low. The last transition occurs at the center of the bit cell if the last bit is a 1, or at the boundary of the bit cell if the last bit is 0. Decoding is accomplished by a differential input receiver circuit and a phase-locked loop that separate the Manchester-encoded data stream into clock signals and NRZ data. The decoder detects the end of a frame when no more mid bit transitions are detected. Within one and half bit times after the last bit, carrier sense is de-asserted. 3.2.4.3 Transmit Driver and Receiver The AT8989UP integrates all the required signal conditioning functions in its 10Base-T block such that external filters are not required. Only one isolation transformer and impedance matching resistors are needed for the 10Base-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmission signal are attenuated properly. 3.2.4.4 Smart Squelch The smart squelch circuit is responsible for determining when valid data is present on the differential receiver. The AT8989UP implements an intelligent receive squelch on the RXP/RXN differential inputs to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to determine the validity of data on the twisted-pair inputs. The signal at the start of the packet is checked by the analog squelch circuit and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150ns. Finally, the signal must exceed the original squelch level within an additional 150ns to ensure that the input waveform will not be rejected. Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. Valid data is considered to be present until the squelch level has not been generated for a time longer than 200 ns, indicating end of packet. Once good data has been detected, the squelch levels are reduced to minimize the effect of noise, causing premature end-of-packet detection. The receive squelch threshold level can be lowered for use in longer cable applications. This is achieved by setting bit 10 of register address 11h. 3.2.5 Carrier Sense Carrier Sense (CRS) is asserted due to receive activity once valid data is detected via the smart squelch function. For 10 Mbps half duplex operation, CRS is asserted during either packet transmission or reception. For 10 Mbps full duplex and
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repeater mode operations, the CRS is asserted only due to receive activity. 3.2.6 Collision Detection The RMII does not have a collision pin. Collision is detected internal to the MAC, which is generated by an AND function of TXEN and CRS derived from CRSDV. CRSDV cannot be directly ANDed with TXEN, because CRSDV may toggle at the end of a frame to provide separation between CRS and RXDV. The internal MII will still generate the COL signal, but this information is not passed to the AMC via the RMII. 3.2.7 Jabber Function The jabber function monitors the AT8989UP output and disables the transmitter if it attempts to transmit a longer than legal sized packet. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled. Once disabled by the jabber function, the transmitter stays disabled for the entire time that the TXEN signal is asserted. This signal has to be de-asserted for approximately 256 ms (The un-jab time) before the jabber function re-enables the transmit outputs. The jabber function can be disabled by programming bit 4 of register address 10h to high. 3.2.8 Link Test Function A link pulse is used to check he integrity of the connection with the remote end. If valid link pulses are not received, the link detector disables the 10Base-T twisted-pair transmitter, receiver, and collision detection functions. The link pulse generator produces pulses as defined in IEEE 802.3 10Base-T standard. Each link pulse is nominally 100ns in duration and is transmitted every 16 ms, in the absence of transmit data. 3.2.9 Automatic Link Polarity Detection AT8989UP's 10Base-T transceiver module incorporates an "automatic link polarity detection circuit". The inverted polarity is determined when seven consecutive link pulses of inverted polarity or three consecutive packets are received with inverted end-of-packet pulses. If the input polarity is reversed, the error condition will be automatically corrected and reported in bit 5 of register 10h. 3.2.10 Clock Synthesizer The AT8989UP implements a clock synthesizer that generates all the reference clocks needed from a single external frequency source. The clock source must be a TTL level signal at 25 MHz +/- 50ppm
3.3 Auto Negotiation
The Auto Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. Fast Link Pulse (FLP) Bursts provide the signaling used to communicate auto negotiation abilities between two devices at each end of a link segment. For further detail regarding auto negotiation, refer to Clause 28 of the IEEE 802.3u specification. The AT8989UP supports four different Ethernet protocols, so the inclusion of auto negotiation ensures that the highest performance protocol will be selected based on the ability of the link partner. Highest priority relative to the following list. 1. 100Base-TX full duplex (highest priority) 2. 100Base-TX half duplex 3. 10Base-T full duplex
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10Base-T half duplex (lowest priority)
3.4 Switch Functional Description
The AT8989UP uses a "store & forward" switching approach for the following reason: Store & forward switches allow switching between different speed media (e.g. 10BaseX and 100BaseX). Such switches require the large elastic buffer especially bridging between a server on a 100Mbps network and clients on a 10Mbps segment. Store & forward switches improve overall network performance by acting as a "network cache" Store & forward switches prevent the forwarding of corrupted packets by the frame check sequence (FCS) before forwarding to the destination port. 3.4.1 Basic Operation The AT8989UP receives incoming packets from one of its ports, searches in the Address Table for the Destination MAC Address and then forwards the packet to the other port within same VLAN group, if appropriate. If the destination address is not found in the address table, the AT8989UP treats the packet as a broadcast packet and forwards the packet to the other ports which in same VLAN group. The AT8989UP automatically learns the port number of attached network devices by examining the Source MAC Address of all incoming packets at wire speed. If the Source Address is not found in the Address Table, the device adds it to the table. 3.4.1.1 Address Learning The AT8989UP uses a hash algorithm to learn the MAC address and can learn up to 2K MAC addresses. Address is stored in the Address Table. The AT8989UP searches for the Source Address (SA) of an incoming packet in the Address Table and acts as below: If the SA was not found in the Address Table (a new address), the AT8989UP waits until the end of the packet (non-error packet) and updates the Address Table. If the SA was found in the Address Table, then aging value of each corresponding entry will be reset to 0. When the DA is PAUSE command, then the learning process will be disabled automatically by AT8989UP. 3.4.1.2 Address Recognition and Packet Forwarding The AT8989UP forwards the incoming packets between bridged ports according to the Destination Address (DA) as below. All the packet forwarding will check VLAN first. Forwarding port must same VLAN with source port. (1) If the DA is an UNICAST address and the address was found in the Address Table, the AT8989UP will check the port number and acts as follows: If the port number is equal to the port on which the packet was received, the packet is discarded. If the port number is different, the packet is forwarded across the bridge. (2) If the DA is an UNICAST address and the address was not found, the AT8989UP treats it as a multicast packet and forwards across the bridge. (3) If the DA is a Multicast address, the packet is forwarded across the bridge. (4) If the DA is PAUSE Command (01-80-C2-00-00-01), then this packet will be dropped by AT8989UP. AT8989UP can issue and learn PAUSE command. (5) AT8989UP will forward the packet with DA of ( 01-80-C2-00-00-00 ), filter out the packet with DA of
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( 01-80-C2-00-00-01 ), and forward the packet with DA of ( 01-80-C2-00-00-02 ~ 01-80-C2-00-00-0F ) 3.4.1.3 Address Aging Address aging is supported for topology changes such as an address moving from one port to the other. When this happens, the AT8989UP internally has a 300 seconds timer will aged out (remove) the address from the address table. Aging function can enable/disable by user. Normally, disabling aging function is for security purpose. 3.4.1.4 Buffers and Queues The AT8989UP incorporates nine transmit queues and receive buffer area for the nine ETHERNET ports. The receive buffers as well as the transmitted queues are located within the AT8989UP along with the switch fabric. The buffers are divided into 448 blocks of 256 bytes each. The queues of each port are managed according to each port's read/write pointer. Input buffers and output queues are maintained through ATAN proprietary patent pending UNIQUE (Universal Queue management) scheme. 3.4.1.5 Back off Algorithm The AT8989UP implements the truncated exponential back off algorithm compliant to the 802.3 CSMA-CD standard. AT8989UP will restart the back off algorithm by choosing 0-9 collision counts. The AT8989UP resets the collision counter after 16 consecutive retransmit trials. 3.4.1.6 Inter-Packet Gap (IPG) IPG is the idle time between any two successive packets from the same port. The typical number is 96 bits time. The value is 9.6us for 10Mbps ETHERNET, 960ns for 100Mbps fast ETHERNET and 96ns for 1000M. AT8989UP provide option of 92 bit gap in EEPROM to prevent packet lost when turn off Flow Control and clock P.P.M. value difference. 3.4.1.7 Illegal Frames The AT8989UP will discard all illegal frames such as runt packet (less than 64 bytes), oversize packet (greater than 1518 or 1522 bytes) and bad CRC. Dribbling packing with good CRC value will accept by AT8989UP. 3.4.1.8 Half Duplex Flow Control Back Pressure function is supported for half-duplex operation. When the AT8989UP cannot allocate a receive buffer for an incoming packet (buffer full), the device will transmit a jam pattern on the port, thus forcing a collision. Back Pressure is enabled by the BPEN set during RESET asserting. An ATAN proprietary algorithm is implemented inside the AT8989UP to prevent back pressure function cause HUB partitioned under heavy traffic environment and reduce the packet lost rate to increase the whole system performance. 3.4.1.9 Full Duplex Flow Control When full duplex port run out of its receive buffer, a PAUSE packet command will be issued by AT8989UP to notice the packet sender to pause transmission. This frame based flow control is totally compliant to IEEE 802.3x. AT8989UP can issue or receive pause packet.
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3.4.1.10 Broadcast Storm filter If Broadcast Storming filter is enable, the broadcast packets over the rising threshold within 50 ms will be discarded by the threshold setting. See EEPROM Reg.10h. Broadcast storm mode after initial: - Time interval : 50ms the max. packet number = 7490 in 100Base, 749 in 10Base Per Port Rising Threshold 00 All 100TX Not All 100TX Disable Disable 01 10% 1% 10 20% 2% 11 40% 4% All 100TX Not All 100TX Per Port Falling Threshold 00 Disable Disable 01 5% 0.5% 10 10% 1% 11 20% 2%
3.4.2 Auto TP MDIX function The traditional method to connect switches and NIC cards is to use one-by-one TP cables. If Switch connects other devices such as another Switch, it must be done by two ways. First is to use Cross-Over TP cable. Second is to use extra RJ45 connector which crossovers internal TX+- and RX+- signal, so-called Uplink port on the front panel of traditional network equipments. Those need extra cost and are not good solution for home-users. AT8989P provides Auto MDIX function which can adjust TX+- and RX+- at correct pin. User can use one-by-one cables between AT8989P and other devices on every port. This function can be Enabled/Disabled by hardware pin or EEPROM option. 3.4.3 Port Locking Port locking function will provide customer simple way to limit per port user number to one. If this function is turn on then AT8989UP will lock first MAC address in learning table. After this MAC address locking will never age out except Reset signal. Another MAC address which not same as locking one will be dropped. AT8989UP provide one MAC address per port. This function is per port setting. When turn on Port Locking function, recommend customer turn off aging function. 3.4.4 Trunk Port AT8989UP supports one Trunk port formed by two 10/100 ports to achieve 400Mbps bandwidth. Those two ports are port 6, and port 7, the last two ports. The trunk function supports Fault tolerance in which the packet will be routed into the other port when either port 6 or port 7 cable disconnect/link fail. Trunk function can set by hardware or EEPROM. EEPROM setting has a higher priority than strapping-pin setting. 3.4.5 VLAN setting & Tag/Untag & port_based VLAN AT8989UP supports bypass mode and untagged port as default setting while the chip is power-on. Thus, every packet with or without tag will be forwarding to the destination port without any modification by AT8989UP. Meanwhile port-base VLAN could be enabled according to the PVID value ( 4bits to map 16 groups written at register 13 to register 22 ) of the configuration content of each port. AT8989UP supports 16 VLAN groups. AT8989UP will recognize the last four bits of total twelve VLAN IDs. If user need to use this function, two EEPROM registers are needed to be programmed first : * Port VID number at EEPROM register 0x1~0x9 bit 13~10: AT8989UP will check the coming packets and will add
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the four bytes VLAN tag to the non-VLAN packets. The LSB of VID will be inserted by the four-bit value. * VLAN Group Mapping Register. EEPROM register 013h~022h defines VLAN grouping value. User uses these registers to define VLAN groups. User can define each port as Tag port or Untag port by register Bit 4. The operation of the communication of packets between Tag port and Untag port can be explained by the following examples: Example1: A port receives Untag packets and sends to an Untag port. AT8989UP will check the port VLAN ID first, then check VLAN group resister. If destination port same VLAN as receiving port then this packet will forward to destination port without any change. If destination port not same VLAN as receiving port then this packet will be dropped. Example2: A port receives Untag packets and sends to a Tag port. AT8989UP will check the port VLAN ID first then check VLAN group resister. If destination port same VLAN as receiving port than this packet will forward to destination port with four byte VLAN Tag and new CRC. If destination port not same VLAN as receiving port then this packet will be dropped. Example3: Port receives Tag packet and send to an Untag port. AT8989UP will check the packet VLAN ID first then check VLAN group resister. If destination port same VLAN as receiving port than this packet will forward to destination port after remove four bytes with new CRC error. If destination port not same VLAN as receiving port then this packet will be dropped. Example4: Port receives Tag packet and send to a Tag port. AT8989UP will check the packet VLAN ID first then check VLAN group resister. If destination port same VLAN as receiving port than this packet will forward to destination port after remove without any change. If destination port not same VLAN as receiving port then this packet will be dropped. 3.4.6 Priority Setting Switch devices not only handle with data packets but also provide services of multimedia data. AT8989UP provides four priority queues on each port at fixed 8:4:2:1 rate. This priority function can set three ways as below: * By Port Base: Set specific port at specific queue. AT8989UP only check the port priority and not check VLAN and TOS. * By VLAN first: AT8989UP check VLAN three priority bit first then TOS priority bits. * By IP TOS first: AT8989UP check IP TOS three priority bit first then VLAN three priority bits. User can set drop low-priority queue ( Q0, Q1 & Q2) when buffer full. This function is optional. 3.4.7 Buffer Management AT8989UP has embedded 1M bit SSRAM for the cost-sensitive market. Since most of packets have length of 256bytes less at real network environment, AT8989UP is designed as 256bytes/block of internal memory. The packets with less 256 bytes length will occupy one block. And AT8989UP will link 2~6 blocks to store the packets of more then 256bytes. This buffer management will provide a better memory utilization on the limited memory size and get a better performance on the real network application.
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3.4.8 LED Display Three LEDs per port are provided by AT8989UP. Link/Act, Duplex/Col & Speed are three LED display of AT8989UP. Dual color LED mode is also supported by AT8989UP. For the easy production purpose AT8989UP will send test signals to each LED one by one at power-on-reset. EEPROM register 0x12h defines the LED configuration table. AT8989UP/GP LED is active Low signal. Dupcol0 & Dupcol1 will check the pin-setting at Reset time. If the pin-setting add a pull high resistor then LEDs will active Low. If the pin-setting add a pull down resister, LEDs will drive high.
Single Color Mode
D? VC C LED
R? LED-High
510
Dual
R? Link/ Act
Color
510
Mode
D? Speed LED
D?
LED
3.5 AT8989UP 16 Port Wire-Speed Switch Application
AT8989UP provides eight ports 100/10 Half/Full port plus one expansion bus with bandwidth up to 1.6Gbps. Two AT8989UPs can connect each other with the expansion bus to be a 16-port wire-speed Switching Hub. The expansion bus is implemented by the existing GMII interface at 100Mhz. Such configuration could get good result at both of Novell's Performance test and the HOL on smart-bit AST, even though it will increase latency around 12% across chips.
3.6 EEPROM Content
EEPROM provides AT8989UP many options setting such as: * Port Configuration: Speed, Duplex, and Flow Control Capability. * Special MII Register programming. * VLAN & TOS Priority Mapping * Broadcast Storming rate * Fiber Select, Auto MDIX select * VLAN Mapping * Per Port Buffer number EEPROM Registers Register 0x00h 0x01h 0x02h 0x03h 0x04h 0x05h 0x06h 0x07h 0x08h 0x09h Bit 15- 8 Signature Port 0 Configuration Port 1 Configuration Port 2 Configuration Port 3 Configuration Port 4 Configuration Port 5 Configuration Port 6 Configuration Port 7 Configuration Port 8 Configuration Bit 7 - 0 Signature Port 0 Configuration Port 1 Configuration Port 2 Configuration Port 3 Configuration Port 4 Configuration Port 5 Configuration Port 6 Configuration Port 7 Configuration Port 8 Configuration Default Value 4154h 40fh 40fh 40fh 40fh 40fh 40fh 40fh 40fh 40fh
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0x0ah 0x0bh 0x0ch 0x0dh 0x0eh 0x0fh 0x10h 0x11h 0x12h 0x13h 0x14h 0x15h 0x16h 0x17h 0x18h 0x19h 0x1ah 0x1bh 0x1ch 0x1dh 0x1eh 0x1fh 0x20h 0x21h 0x22h 0x23h 0x24h 0x25h 0x26h 0x27h
Configuration Customized MII Register for Port 8 Port 0 ~ 7 MII Data High Port 8 MII Data High VLAN priority Map High TOS priority Map High Miscellaneous Configuration 0 Reserved Miscellaneous Configuration 1 VLAN 0 outbound Port Map VLAN 1 outbound Port Map VLAN 2 outbound Port Map VLAN 3 outbound Port Map VLAN 4 outbound Port Map VLAN 5 outbound Port Map VLAN 6 outbound Port Map VLAN 7 outbound Port Map VLAN 8 outbound Port Map VLAN 9 outbound Port Map VLAN 10 outbound Port Map VLAN 11 outbound Port Map VLAN 12 outbound Port Map VLAN 13 outbound Port Map VLAN 14 outbound Port Map VLAN 15 outbound Port Map P1 Buffer Threshold P3 Buffer Threshold P5 Buffer Threshold P7 Buffer Threshold Threshold Sel Total Buffer Threshold
Configuration Customized MII Register for Port 0~7 Port 0 ~ 7 MII Data Low Port 8 MII Data Low VLAN priority Map Low TOS priority Map Low Miscellaneous Configuration 0 Reserved Miscellaneous Configuration 1 VLAN 0 outbound Port Map VLAN 1 outbound Port Map VLAN 2 outbound Port Map VLAN 3 outbound Port Map VLAN 4 outbound Port Map VLAN 5 outbound Port Map VLAN 6 outbound Port Map VLAN 7 outbound Port Map VLAN 8 outbound Port Map VLAN 9 outbound Port Map VLAN 10 outbound Port Map VLAN 11 outbound Port Map VLAN 12 outbound Port Map VLAN 13 outbound Port Map VLAN 14 outbound Port Map VLAN 15 outbound Port Map P0 Buffer Threshold P2 Buffer Threshold P4 Buffer Threshold P6 Buffer Threshold P8 Buffer Threshold
0h 8000h fa50h fa50h fa50h fa50h aa40h ff00h 3600h 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 0h 0h 0h 0h 0h
Signature Register:0x00h Configuration
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Description
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Bit [15:0]
The value must be 4154h(AT)
Configuration Registers: Register 0x01h ~ 0x09h Configuration Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit [9:8] Bit [13:10] Bit[14] Bit [15] Configuration: Register 0x0ah Configuration Bit [7:0] Bit 8 Bit 9 Bit [15:10] Description Reserve Reserve Enable Replace VLAN ID 0 &1 by PVID Reserved Description 802.3x Flow control command ability Auto negotiation Enable. High enable, Low disable Speed. High 100TX, Low 10 Base-T Duplex. High Full, Low Half VLAN Tag or UnTag Port Reserve TOS over VLAN priority Enable port-base priority Port-base priority PVID. Port base VLAN ID Select FX Crossover auto-detect enable
Customized MII Address Register: Register 0x0bh Configuration Bit [4:0] Bit 5 Bit 6 Bit 7 Bit [12:8] Bit 13 Description Port 0~7 MII Register Address Port 0~7 MII Write Enable. High Active Enable IPG leveling Enable Trunk Port Port 8 MII Register Address Port 8 MII Write Enable. High Active
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Bit 14 Bit 15
Reserve Reserve
Customized MII Data Register: Register 0x0ch Configuration Bit [15:0] Description Port 0~7 MII Data
Customized MII Data Register: Register 0x0dh Configuration Bit [15:0] Description Port 8 MII Data
VLAN( TOS) priority Map: Register 0x0eh ( VLAN), 0x0fh( TOS) Configuration Bit [1:0] Bit [3:2] Bit [5:4] Bit [7:6] Bit [9:8] Bit [11:10] Bit [13:12] Bit [15:14] Description Mapped priority of tag value(VLAN, TOS) 0 Mapped priority of tag value(VLAN, TOS) 1 Mapped priority of tag value(VLAN, TOS) 2 Mapped priority of tag value(VLAN, TOS) 3 Mapped priority of tag value(VLAN, TOS) 4 Mapped priority of tag value(VLAN, TOS) 5 Mapped priority of tag value(VLAN, TOS) 6 Mapped priority of tag value(VLAN, TOS) 7
00: lowest priority queue. Q0 01: lower priority queue. Q1 10: higher priority queue. Q2 11: highest priority queue. Q3 The weight ratio is Q0: Q1: Q2: Q3=1: 2: 4: 8. The default is Q1 for un-tag packet and none IP frame. Miscellaneous Configuration: Register 0x10h Configuration Bit [1:0] Bit [2] Bit [3] Bit [4] Bit [5]
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Description Broadcast Storming Threshold[1:0] Broadcast Storming Enable Reserve XCRC (0/XCRCCHK, enable CRC Check) Reserve
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Bit [6] Bit [7] Bit [15:8]
SWCLK (switch rxclk to txclk for 7-wire) Aging Disable. Reserve
VLAN mode select Register: Register 0x11h, default value is 0xff00h : Configuration Bit [4:0] Bit [5] Description Reserved, default value 0 VLAN mode select, default 0 0 : by-pass mode with port-base VLAN 1 : VLAN ID base VLAN. Bit [7:6] Bit [15:8] Reserved. Default value 0 Reserved, default value 1
Miscellaneous Configuration: Register 0x12h Configuration Bit [8:0] Bit [10:9] Bit [11] Bit [13:12] EDI, Bit [14] Description Unilrn8~0 (for security mode) Reserve Reserve Power Saving Select Recommend LED variety Lnkact 00 01 10 11 VLAN mapping table register: 0x13h~0x22h Configuration Bit [8:0] Per Port Buffer Threshold: 0x23h~0x26h Configuration Description
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Speed Single color Single color Dual color Dual color
Dupcol (always single color) Duplex/col duplex Duplex/col duplex
Single color Single color Dual color Dual color
Description VLAN mapping table.
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Bit [13:8], Bit [5:0] Total Buffer Threshold: 0x27h Configuration Bit [5:0] Bit 7
Port Buffer Threshold (available buffers are 8 times of the value)
Description Total Buffer Threshold for all ports 1: Enable EEPROM Threshold value, 0: default Threshold value
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4. EEPROM Content Description
4.1 EEPROM Register Description:
Register 0x00h: Signature. Default value is 4154h. AT8989UP will check register 0 value before read EEPROM content. If this value do not match with 4154h then other values in EEPROM will be useless. AT8989UP will use internal defaulted value. Register 0x01h~0x09h: Port 0~8 configuration register. Bit 0: 802.3X Flow Control capability. 1: Enable; 0: Disable. Bit 1: Auto Negotiation capability Enable. 1: Enable; 0: Disable. Bit 2: Speed Capability when Bit 1 Enable. 1: 100; 0: 10. Bit 3: Duplex Capability when Bit 1 Enable. 1: Full; 0: Half. Bit 4: VLAN Tag Port. 1: set to Tag port; 0: set to Untag port. Bit 5: Reserve. Bit 6: TOS over VLAN Priority. Define AT8989UP priority source when VLAN & TOS existed in the packet. 1: TOS priority level higher than VLAN; 0: VLAN priority level higher than TOS. (default) Bit 7: Enable Port Based Priority. 1: Enable; 0: Disable. If this bit turn on, AT8989UP will not check TOS or VLAN as priority reference. AT8989UP will check port base priority only. Bit[9:8]: Port base priority number. From 0~3 mapping to Q0~Q3. Bit[13~10]: Port Base VLAN ID when packet without 4 bytes VLAN tag. If packet with 4 bytes VLAN then AT8989P will not add this VLAN ID to packet content. ID is from 0-15. Bit[14]: Select FX interface. 1: FX; 0: TP; Bit[15]: Auto MDIX enable. 1: Enable; 0: Disable. Register 0x0ah: Configuration register. Bit[7~0]: Reserve. Bit 8: Reserve. Bit 9: To replace VLAN ID 0 & 1 by PVID. 1: Enable; 0: Disable. If this bit enable then AT8989UP will check VLAN ID. If this VLAN ID is 0 or 1 then AT8989UP will replace this ID by PVID. Bit[15~10]: Reserved. Register 0x0bh: Custom MII Address Register Bit[4~0]: Reserve. Bit 5: Reserve. Bit 6: Enable IPG Leveling. 1: Enable. 0: Disable. When this bit is enabled, AT8989UP will transmit packet out with 92 bit-time of IPG for test under SmartBit. If disable this function AT8989UP will transmit packet with 96 bit-time IPG for normal application. Bit 7: Trunk port enable. 1: Enable, 0: Disable. If enable, these Trunk port must be set at the same VLAN. The speed must run at 100M Full Duplex, regardless of
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other previous settings. Bit[15~8]: Reserve. Register 0x0ch: Reserve. Register 0x0dh: Reserve. Register 0x0eh: VLAN priority map Value 00~11 are Q0~Q3 respectively. Bit[1:0]: Mapped priority of VLAN tag value 0 Bit[3:2]: Mapped priority of VLAN tag value 1 Bit[5:4]: Mapped priority of VLAN tag value 2 Bit[7:6]: Mapped priority of VLAN tag value 3 Bit[9:8]: Mapped priority of VLAN tag value 4 Bit[11:10]: Mapped priority of VLAN tag value 5 Bit[13:12]: Mapped priority of VLAN tag value 6 Bit[15:14]: Mapped priority of VLAN tag value 7 Register 0x0fh: TOS priority map Value 00~11 are Q0~Q3 respectively. Bit[1:0]: Mapped priority of TOS value 0 Bit[3:2]: Mapped priority of TOS value 1 Bit[5:4]: Mapped priority of TOS value 2 Bit[7:6]: Mapped priority of TOS value 3 Bit[9:8]: Mapped priority of TOS value 4 Bit[11:10]: Mapped priority of TOS value 5 Bit[13:12]: Mapped priority of TOS value 6 Bit[15:14]: Mapped priority of TOS value 7 Register 0x10h: Miscellaneous Configuration Register. Bit[1:0]: Broadcast Storming threshold. See Broadcast Threshold table. Bit 2: Broadcast Storming Enable. 0: Disable. 1: Enable. Bit 3: Reserve. Bit 4: CRC check disable. 1: Disable. 0: Enable. Bit 5: Reserve. Bit 6: Switch RXCLK to TXCLK at GPSI interface. 1: Enable. 0: Disable. Bit 7: Aging Disable. 1: Disable. 0: Enable. Bit[15:8]: Reserve. Register 0x11h: Bit 5: VLAN mode select, default is "0". "0", By-pass mode with port-base VLAN. "1", VLAN ID base VLAN. Bit [15:6] : Reserve value "1", Bit [4:0] : Reserve value "0".
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Register 0x12h: Miscellaneous Configuration Register Bit 6: Enable IPG Leveling. 1: Enable. 0: Disable. Bit [8:0]: Port Locking enable. Learn one MAC ID when enable. 1: Enable. 0: Disable. Bit [10:9]: Reserve. Bit 11: Reserve. Bit [13:12]: Power Saving. 1: Enable. 0: Disable. Bit[14]: LED selection. See EEPROM content. Bit[15]: ENDC16 select excessive collision drop packet. 1: drop. 0: no drop. Register 0x22h~0x13h: VLAN group 15~0 outbound port map. Default value 1ffh. Each register bit0~8 directly point to port 0~8. Select the VLAN group ports is to set the corresponding bits to 1. Register 0x26h~0x23h: Bit[5:0] Port 7~0 Buffer Threshold when register 0x27h bit 15=1. Normal value is 03h. Register 0x27h: Bit[5:0]: Port 8 buffer Threshold. Bit[12:8]: total buffer Threshold. Bit 15: Threshold selection enable. 1: Enable; 0: Disable. When set at "1", AT8989UP will set buffer threshold by the value of register0x26h~0x23h. Packet with Priority: Normal packet content Ethernet Packet from Layer 2
Preamble/SFD Destination (6 bytes) Source (6 bytes) Packet length (2 bytes) Data (46-1500 bytes) CRC (4 bytes)
Byte 0~5 VLAN Packet
Byte 6~11
Byte 12~13
Byte 14~
AT8989UP will check packet byte 12 &13. If byte[12:13]=8100h then this packet is a VLAN packet Tag Protocol TD 8100 Byte 12~13 Tag Control Information TCI LEN Length Byte14~15 Byte 16~17 Routing Information Byte 18
Byte 14~15: Tag Control Information TCI Bit[15:13]: User Priority 7~0 Bit 12: Canonical Format Indicator (CFI) Bit[11~0]: VLAN ID. The AT8989UP will use bit[3:0] as VLAN group. TOS IP Packet AT8989UP check byte 12 &13 if this value is 0800h then AT8989UP knows this is a TOP priority packet.
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Type 0800 Byte 12~13
IP Header Byte 14~15
IP header define Byte 14 Bit[7:0]: IP protocol version number & header length. Byte 15: Service type Bit[7~5]: IP Priority (Precedence ) from 7~0 Bit 4: No Delay (D) Bit 3: High Throughput Bit 2: High Reliability (R) Bit[1:0]: Reserve
4.2 EEPROM Access
Customer can select AT8989UP read EEPROM contents as chip setting or not. AT8989UP will check the signature of EEPROM to decide read content of EEPROM or not. RESETL & EEPROM content relationship RESETL CS SK DI DO
0 Rising edge 0 1 (30ms) 1 (after 30ms) Input Input Input Input High Impedance Output High Impedance Output High Impedance Output High Impedance Output
Keep at least 30ms after RESETL from 0 1. AT8989UP will read data from EEPROM. After RESETL=1, AT8989UP will update configuration registers too if CPU update EEPROM. When CPU programs EEPROM & AT8989UP, AT8989UP will recognize the EEPROM WRITE instruction only. If there is any Protection instruction before or after the EEPROM WRITE instruction, CPU needs to generate a separated CS signal cycle for each Protection & WRITE instruction. CPU can directly program AT8989UP after 30ms of Reset signal rising edge with or without the presence of EEPROM.
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5. DC Characteristics
5.1 Absolute Maximum Rating
Symbol VCCxx Vcca2 Vccpll Vccik VIN Vout TSTG PD Tc ESD Symbol Vcc Vcca2 Vccpll Vccik Vin PC Tj Parameter Power Supply TX line driver PLL voltage Digital core voltage Input Voltage Output Voltage Storage Temperature Power Dissipation Temperature of Package Case Surface ESD Rating Parameter Power Supply TX line driver PLL voltage Digital core voltage Input Voltage Power consumption Junction Operating Temperature Rating -0.3 to 3.63 -0.3 to 2.75 -0.3 to 2.75 -0.3 to 2.75 -0.3 to VCC + 0.3 -0.3 to Vcc + 0.3 -55 to 155 4 150 2KV Min 3.135 Typ 3.3 2.25 2.25 2.25 2.6 25 Max 3.465 Units V V V V V V C W C V Units V V V V V W C
5.2 Recommended Operating Conditions
0 0
Vcc
5.3 DC Electrical Characteristics for 3.3V Operation
(Under Vcc=3.0V~3.6V, Tj= 0 C ~ 125 C ) Symbol VIL VIH VOL VOH RI Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Pull_up/down Resistance Conditions CMOS CMOS CMOS CMOS VIL=0V or VIH = Vcc Min 0.7 * Vcc 0.7 * Vcc 100 Typ Max Units 0.3 * Vcc V V 0.4 V V K
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6. AC Characteristics
6.1. GRXD7_0, GRXDV, GRXER and GRXCLK Receive Signals Timing
GRXCLK
GRXD[7::0], GRXDV T10 T11
Name T10 T11
Parameter Setup Time to Rising GRXCLK Hold Time to Rising GRXCLK
Min 4 2
Max
Units ns ns
GRXCLK Freq/125MHz, Period/8+- 0.5ns, GRXCLK high/2.5ns min, GRXCLK low/2.5ns min
6.2. GTXD7_0, GTXEN, GTXER and GTXCLK Transmit Signals Timing
GTXCLK
GTXD[7:0] GTXEN T20
Name T20
Parameter Data Valid Delay after Rising GTXCLK
Min 1.5
Max 4
Units ns
GTXCLK Freq/125MHz, Period/8+- 0.5ns, GTXCLK high/2.5ns min, GTXCLK low/2.5ns min
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6.3 EECS, EESK and EDI Signals Timing
EESK
EECS
T60 EESK
EDI T62 T61
Name T60 T61 T62
Parameter EECS to EESK setup time EDI to EESK setup time EDI to EESK hold time
Min 10 10 10
Max
Units ns ns ns
6.4 Expansion bus 1.6G Receive Signals Timing
GRXCLK
GRXD[7::0], GRXDV T10 T11
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Name T10 T11
Parameter Setup Time to Rising GRXCLK Hold Time to Rising GRXCLK
Min 4 2
Max
Units ns ns
6.5 Expansion 1.6G Transmit Signals Timing
GTXCLK
GTXD[7:0] GTXEN T20
Name T20
Parameter Data Valid Delay after Rising GTXCLK
Min 1.5
Max 4
Units ns
6.6MII Receive Signals Timing
RXCLK
RXD[3::0], RXDV T10 T11
Name T10 T11
Parameter Setup Time to Rising RXCLK Hold Time to Rising RXCLK
Min 4 2
Max
Units ns ns
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6.7MII Transmit Signals Timing
TXCLK
TXD[3:0] TXEN T20
Name T20
Parameter Data Valid Delay after Rising TXCLK
Min 3
Max 10
Units ns
6.8 PSI(7 wires) Transmit Signals Timing
TXC
TXEN T30 T31
TXD0
T32
T33
Name T30 T31 T32 T33
Parameter Transmit Enable Setup Time to TXC Rising Transmit Enable Hold Time to TXC Rising Transmit Data Setup Time to TXC Rising Transmit Data Hold Time to TXC Rising
Min 20 5 20 5
Max
Units ns ns ns ns
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GPSI (7 wires) Receive Signals Timing
RXC
5 Extra CRS T40 T41 Clocks
RXD0
Name T40 T41
Parameter Receive Data Setup Time to RXC Rising Receive Data Hold Time to RXC Rising
Min 10 5
Max
Units ns ns
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7. Package
208 Pin PQFP Outside Dimension
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